1. Technical Field
The present invention relates to a semiconductor device and a method of fabricating a semiconductor device.
2. Related Art
In recent years, in the field of information devices typified by a cellular phone and a digital camera, miniaturization, higher density, and higher performance of a device are in demand. As a technique realizing them, a wafer level chip size package (hereinbelow, called W-CSP) for fabricating a semiconductor device built in those devices by the same package as that of the chip size is known. The W-CSP is a package of a new concept that all of assembling processes are completed in a wafer state. Since the chip area is effectively used by rewiring technique and external electrodes are formed in the entire surface of a semiconductor device, space of wire bonding as the conventional wiring method is unnecessary. Consequently, the area of a completed package has the same size as the chip size and, moreover, mounting to a mounting board is easy, so that the package is suitable for high-density mounting.
A semiconductor device having the W-CSP structure is fabricated by, for example, the following procedure. First, an insulating film is formed on a semiconductor substrate on which circuit devices such as transistors, electrode pads, and the like are formed. Next, an opening is formed in the insulating film to partially expose the electrode pad formed on the semiconductor substrate. A rewiring layer electrically connected to the electrode pad in the opening in the insulating film is formed on the insulating film. A mold resin is formed on the semiconductor substrate so as to cover the rewiring layer. After that, an opening is formed in the mold resin to partially expose the rewiring layer. Finally, an external connection terminal such as a solder bump is formed on the exposed rewiring layer. By the above processes, the semiconductor device having the W-CSP structure is completed.
In a process of fabricating a semiconductor substrate prior to execution of the above-described fabricating processes, an electric test for confirming a circuit operation is conducted. In the test process, a test is conducted by making a probe of a tester come into contact with the electrode pad formed on the semiconductor substrate. Consequently, there is a case that a projected probe mark is formed in the surface of the electrode pad. In the case where the electrode pad with which the test probe comes into contact and the electrode pad to which the rewiring layer is connected are provided independently of each other, the rewiring layer is not connected to the electrode pad for a test, so that the surface of the electrode pad for a test is covered with an insulating film. However, when a projected probe mark is formed in the surface of the electrode pad for a test, adhesion between the insulating film and the electrode pad deteriorates. When moisture or the like enters the package, the electrode pad for a test becomes corroded and, moreover, there is the possibility that an internal circuit formed on the semiconductor substrate is also damaged.
Japanese Patent Application Laid-Open (JP-A) No. 2004-296775 describes that the problem can be solved by covering the electrode pad for a test with which a test probe comes into contact with the rewiring layer.
As the performances of information devices are becoming higher in recent years, there is a case that a wafer test is conducted plural times. In this case, the test probe comes into contact with the electrode pad plural times. The height of the projected probe mark formed in the surface of the electrode pad increases as the number of test times increases. In a circumstance that a probe mark having a relatively tall projection is formed in the surface of an electrode pad, when the structure that the electrode pad for a test is covered with the rewiring layer as described in JP-A No. 2004-296775 is employed, the following problem may occur. Generally, the rewiring layer covering the surface of the electrode pad is made of Cu or the like and formed by electrolytic plating. In the case of forming the rewiring layer by electrolytic plating, a plating seed layer has to be formed below the rewiring layer. The plating seed layer can be formed by sputtering. However, when a projected probe mark is formed in the surface of the electrode pad and, moreover, the projection is tall, coverage of the plating seed layer deteriorates. Since the rewiring layer cannot be formed in a part where the plating seed layer is missing, it becomes difficult to completely cover the probe mark formed in the electrode pad with the rewiring layer. A structure that the electrode pad and a mold resin are in direct contact via the projection of the probe mark is resulted. In such a structure, when moisture or the like enters the package, corrosion in the electrode pad progresses via the projection of the probe mark. Further, the adverse influence may be exerted on the operational characteristics of an integrated circuit formed on the semiconductor substrate, and it is an issue from the viewpoint of reliability. On the other hand, a structure of thickly forming an insulating film so as to completely cover a projected probe mark formed in the surface of the electrode pad may be also employed. In this case, however, it is difficult to form a contact hole for connecting the rewiring layer and the electrode pad.